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Fix lmul for vsext and vzext #28

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merged 2 commits into from
Feb 5, 2024
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@troibe troibe commented Feb 5, 2024

The way I read the following lines in the spec is that for vsext.vf4 or vzext.vf4 source eew (=sew/4=16) and emul (=lmul/4=1/2) are smaller than the destination eew (=sew=64) and emul (=lmul=2).

The EEW of the source is 1/2, 1/4, or 1/8 of SEW, while EMUL of the source is (EEW/SEW)*LMUL. The destination has EEW equal to SEW and EMUL equal to LMUL.

Fixed #26

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ksco commented Feb 5, 2024

Ah yes, it's the other way around, sorry. But I think my original proposal still is the correct fix -- vdEMUL is for vd, c.LMUL1 is for vs2.

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ksco commented Feb 5, 2024

Oh no wait, sorry, the vdEMUL is indeed wrongly calculated.

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There are 4 variables involved:

  1. vd EMUL: c.LMUL1
  2. vd EEW: c.SEW
  3. vs2 EMUL: vs2EMUL
  4. vs2 EEW: vs2EEW

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troibe commented Feb 5, 2024

Thanks for the feedback!

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Thanks

@ksco ksco merged commit c2dcdc4 into chipsalliance:main Feb 5, 2024
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Tests for vsext.vf4/8 and vzext.vf4/8 rely on inital values of vector registers
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